1. Field of the Invention
The present invention relates to non-volatile memory arrays and, in particular, to a flash memory array architecture that utilizes a time-shared address bus and separate memory cell access paths to perform read cycle operations in one memory cell block in the array while an algorithm operation, such as an erase/reprogram operation, is performed simultaneously in another memory cell block in the array. The multiplexed address bus architecture avoids the need for the complex, multiple address bus structures previously required to implement simultaneous read/write operations in a flash memory architecture.
2. Discussion of the Related Art
U.S. Pat. No. 5,245,572, issued on Sep. 14, 1993, to Kosonocky et al., discloses a flash memory architecture that includes two separate memory cell banks that can be simultaneously and individually addressed to perform a read operation in one bank of cells while an erase/reprogram operation is being performed in the other bank of cells.
In the Kosonocky et al. architecture, an address register is provided for storing an address for one of the memory cell banks. A second address register is provided for storing a second address for the second memory cell bank. A multiplexer selectively couples either the first memory cell bank or the second memory cell bank, one at a time, to the memory device output. Array select circuitry that responds to an incoming address signal selects one of the memory cell banks for a reprogramming operation and the other memory cell bank for a read operation. The array select circuitry also controls the multiplexer for coupling the memory cell bank that is being read to the device outputs during the reprogramming of the other memory cell bank.
Advanced Micro Devices Publication #21357, Rev: A, "Am29DL800T/Am29DL800B, 8 Megabit (1M.times.8-bit/512K.times.16-bit) CMOS Volt-only, Simultaneous Operation Flash Memory", May 1997, discloses a flash memory architecture that also provides for simultaneous read/write operations by dividing the memory space into two banks. The AMD device allows a host system to program or erase one memory cell bank, then immediately and simultaneously read from the other bank, with zero latency.
A drawback associated with both the Kosonocky et al. architecture and the AMD architecture is that both rely on separate address bus structures for each of the two memory cell banks and, therefore, are only suitable for a two-bank architectural scheme. Thus, if the simultaneous read/write concept of these architectures is to be expanded to the sector or block level (multiple banks), then the address bus structure necessarily becomes prohibitively complex and write sense amplifiers, program load, data latch and data compare logic must be repeated for each memory cell bank in the array.